Mechatronic Engineering with Industrial Experience (5 Years) [MEng]View content for printing (opens a new page)
EEEN20023 - Digital Systems Design 2
Availability - Course (Compulsory/Elective)
|EEEN10026 Digital System Design I|
This programme unit aims to:
- Enable students to use structured digital system design methods, hardware description languages and verification tools to design digital systems.
- Expose students to practical implementation issues for digital systems.
This unit will cover the following:
- Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.
- Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.
- Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines.
- Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL.
- Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.
- Introduction to Programmable Logic Devices (FPGAs, CPLDs)
Students will be able to:
Knowledge and understanding:
- Gain familiarity with various styles (behavioural, structural and physical) used to describe digital systems
- Understand the top-down design process, progressing through levels of abstraction from high-level system description down to gate-level implementation
- Understand basic concepts behind behavioural system modelling: concurrency and event-driven simulation
- Appreciate system implementation issues such as noise, delays and synchronisation
- Create behavioural VHDL descriptions of basic components and digital systems
- Create synthesisable VHDL descriptions of combinatoral and sequential logic circuits
- Predict the behaviour of a digital system or the simulation result of a piece of VHDL code
- Gain familiarity with VHDL
- Use Electronic Design Automation (EDA) tools competently for digital system design: VHDL design entry, simulation and synthesis
- Implement digital designs using Programmable Logic Devices
Teaching & Learning Process (Hours Allocated To)
Unseen Written Examination:
Three questions, answer all questions
Duration: 1 hour 30 minutes
Calculators are permitted
This examination forms 80% of the unit assessment
Three laboratory sessions
Laboratory duration 3 hours
Coursework assignments associated with Lab 1 and Lab 2 (two sets of assignments)
Coursework must be submited on-line within two weeks of the laboratory taking place.
All theree labortory sessions must be attended
Course work forms 20% of the unit assessment and is both formative and summative
|Dr Piotr Dudek||-||Lecturer|