Low noise integrated compound semiconductor circuits

pHEMT Bottom gate definition and device side view
Figure 1: pHEMT Bottom gate definition and device side view

The main objective of this research is to develop and fabricate low noise amplifier (LNAs) at X and Ka bands using fully on-chip Monolithic Microwave Integrated Circuit (MMIC) technology.

To date, we have developed a novel, low cost 250 nm gate length using i-line lithography which resulted in a current gain cut-off frequency (fT) of 90 GHz. These are about 4.5 times higher than the 1 µm gate device reported previously. The 250 nm gate length is achieved by a low cost, temperature soft reflow process.

 

Single stage LNA mask layout
Figure 2: Single stage LNA mask layout

Further improvement of the soft reflow process is expected to achieve smaller gate length, approaching 100 nm.

A large number ofdevice designs, fabrication and characterization of submicron InGaAs/InAlAs/InP pHEMTs on different gate dimensions (2x50um, 2x100um, and 2x200um) are being carried out. These include optimizations at each critical fabrication steps. The device’s high breakdown and very low gate leakage characteristics will be further improved by a combination of judicious combination of epitaxial growth and manipulation of materials’ energy gaps.

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